Integrated circuits typically include a number of input/output pins which are used for communication with additional circuitry. For example, an integrated memory device, such as a dynamic random access memory (DRAM), includes both control inputs for receiving memory operation control signals, and data pins for bidirectional data communication with an external system or processor.
The data transmission rate of modern integrated circuits is primarily limited by internal circuitry operating speeds. That is, communication networks have been developed which can transmit signals between circuitry at a rate that is faster than the capacity of many integrated circuits. To address the need for faster circuits, a group of integrated circuits can be combined on a common bus and be controlled by a common controller. In this configuration, each integrated circuit operates in a coordinated manner with the other integrated circuits to share data which is transmitted at a high speed. For example, a group of memory devices, such as DRAMs, static RAMs, or read only memories (ROM), can be connected to a common data bus and be controlled by a memory controller to form a memory system. The data rate of the bus may be substantially faster than the feasible operating speed of the individual memories. Each memory, therefore, is operated so that while one memory is processing received data, another memory is receiving new data. Such a memory system with an appropriate number of memory devices and an efficient memory controller can achieve very high speed data transmissions.
As the transmission rate of the data communication signals in such memory systems continues to increase, new circuitry and methods are needed to accurately clock command data, write data, and read data transmitted between the memory controller and the memory devices. The portion of a clock cycle which can be devoted to clocking valid data becomes quite small, and errors in clocking data can occur, at these increased transmission speeds because of known effects such as duty cycle variation, bus position of a given memory device, timing drift, loading variations, clock jitter, clock skew, noise, overshoot, and ringing.
Therefore, for the reasons stated above, and for other reasons presented in greater detail in the Description of the Preferred Embodiments section of the present specification, there is a need in the art for a memory system which more accurately and precisely compensates for such effects as duty cycle variation, bus position of a given memory device, timing drift, loading variations, clock jitter, clock skew, noise, overshoot, and ringing so that data can be accurately clocked in the memory devices.